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2.5 v and 3.3 v cmos pll clock generator and driver mpc9315 rev. 4, 08/2005 freescale semiconductor technical data ? freescale semiconductor, in c., 2005. all rights reserved. 2.5 v and 3.3 v cmos pll clock generator and driver the mpc9315 is a 2.5 v and 3.3 v compatible, pll based clock generator designed for low-skew clock distribution in low-voltage mid-range to high-performance telecom, networking and computing applications. the mpc9315 offers 8 low-skew outputs and 2 selectable inputs for clock redundancy. the outputs are configurable and support 1:1, 2:1, 4:1, 1:2 and 1:4 output to input frequency ratios. in addition, a selectable output 180 phase control supports advanced clocking schem es with inverted cl ock signals. the mpc9315 is specified for the extended temperature range of ?40 to +85 c. features ? configurable 8 outputs lvcmos pll clock generator ? compatible to various microprocessors such as powerquicc i and ii ? wide range output clock fr equency of 18.75 to 160 mhz ? 2.5 v and 3.3 v cmos compatible ? designed for mid-range to high-performance telecom, networking and computer applications ? fully integrated pll supports spread spectrum clocking ? supports applications requiring clock redundancy ? max. output skew of 120 ps (80 ps within one bank) ? selectable output configurations (1:1 , 2:1, 4:1, 1:2, 1:4 frequency ratios) ? two selectable lvcmos clock inputs ? external pll feedback path and selectable feedback configuration ? tristable outputs ? 32-lead lqfp package ? ambient operating temperature range of -40 to +85 c ? 32-lead pb-free package available functional description the mpc9315 utilizes pll technology to frequency and phase lock it s outputs onto an input reference clock. normal operation requires a connection of one of the device outputs to the selected feedback (fb0 or fb1) input to close the pll feedback path. the reference clock frequency and the output divider for the feedba ck path determine the vco frequency. both must be selected to match the vco frequency range. with avail able output dividers of divide-by-1, divide -by-2 and divide-by-4, the internal vco of the mpc9315 is running at ei ther 1x, 2x or 4x of the refe rence clock frequency. the frequency of the qa, qb, qc output group s is either the equal, one half or one fourth of the selected vc o frequency and can be configured for each output bank using the fsela, fselb and fselc pins, respectively. the available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. the ref_sel pin selects one of the two available lvcmos compatible reference input (clk0 and clk1) supporting clock redundant applications. the selectable feedback input pin allows the user to select different feedback configurations and input to output frequency ratios. the mpc9315 also provides a static test mode when the pll supply pin (v cca ) is pulled to logic low state (gnd). in test mode, the select ed input reference clock is routed directly to the output dividers bypassing the pll. the test m ode is intended for system diagnostics, test and debug purposes. this test mode is fully static and the minimum clock frequency spe c- ification does not apply. the outputs can be disabled by deasserting the oe pin (logic high state). in pll mode, deasserting oe causes the pll to lose lock due to no feedback signal presence at fb0 or fb1. asserting oe will enable the outputs and close the phase locked loop, also enabling the pll to recover to norma l operation. the mpc9315 is fu lly 2.5 v and 3.3 v compatible and requires no external loop filter components. all inputs a ccept lvcmos signals while the outputs provide lvcmos compat- ible levels with the capability to drive terminated 50 ? transmission lines. for series termi nated transmission lines, each of the mpc9315 outputs can drive one or two traces giving the devices an effective fanout of 1:18. the device is packaged in a 7x7 mm 2 32-lead lqfp package. the fully integrated pll of the mpc9315 allows the low skew outp uts to lock onto a clock input and distribute it with essential ly zero propagation delay to multiple components on the board. in zero-delay buffer mode, the pll minimizes phase offset between the outputs and the reference signal. mpc9315 low voltage 2.5 v and 3.3 v pll clock generator fa suffix 32-lead lqfp package case 873a-04 ac suffix 32-lead lqfp package pb-free package case 873a-04 data sheet mpc9315 idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 1
idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 2 mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom advanced clock drivers devices 2 freescale semiconductor mpc9315 figure 1. mpc9315 logic diagram figure 2. pinout: 32-lead package pinout (top view) pll (pulldown) fb_sel qa0 qa1 ref_sel clk0 0 1 clk1 ref fb 75 ? 160 mhz clk qc1 qb0 0 1 0 1 fsela fselc v cca v cc 6 (pulldown) (pulldown) fb0 0 1 fb1 (pulldown) (pulldown) (pulldown) (pulldown) qb2 qb3 qc0 qb1 fselb (pulldown) (pullup) (pullup) gnd 6 0 1 psela (pulldown) 0 1 oe bank b bank a bank c clk # 2 clk # 4 gnd qa1 qa0 v cc fselc fselb fsela v cc qc0 qc1 gnd v cc psela v cc qb0 gnd qb1 v cc qb2 gnd qb3 v cc clk0 ref_sel clk1 v cca fb0 fb1 gnd 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 mpc9315 gnd fbsel oe
idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 3 mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom advanced clock drivers devices freescale semiconductor 3 mpc9315 table 1. pin configuration pin i/o type function clk0 input lvcmos reference clock input clk1 input lvcmos alternative clock input fb0 input lvcmos pll feedback input fb1 input lvcmos alternative feedback input ref_sel input lvcmos selects clock input reference cl ock input, default low (pull-down) fb_sel input lvcmos selects pll feedback clock input, default low (pull-down) fsela input lvcmos selects divider ratio of bank a outputs, default low (pull-down) fselb input lvcmos selects divider ratio of bank b outputs, default low (pull-up) fselc input lvcmos selects divider ratio of bank c outputs, default low (pull-up) psela input lvcmos selects phase of bank a outputs qa0, qa1 output lvcmos bank a outputs qb0 to qb3 output lvcmos bank b outputs qc0, qc1 output lvcmos bank c outputs oe input lvcmos output tristate v cca supply analog (pll) positive supply volt age. requires external rc filter v cc supply digital positive supply voltage gnd ground digital negative supply voltage (ground) table 2. function table control default 0 1 ref_sel 0 clk0 clk1 fb_sel 0 fb0 fb1 fsela 0 qax = vco clock frequency qa0, qa1 = vco clock frequency # 2 fselb 1 qbx = vco clock frequency qb0 - qb3 = vco clock frequency # 2 fselc 1 qcx = vco clock frequency # 2 qc0, qc1 = vco clock frequency # 4 psela 0 0 (qa0, qa1 non-inverted) 180 ! (qa0, qa1 inverted) v cca none v cca = gnd, pll off and bypassed for static test and diagnosis v cca = 3.3 or 2.5 v, pll enabled mr 0 normal operation reset (vco clamped to min. range) oe 0 outputs enabled outputs disabled (tristate), open pll loop table 3. absolute maximum ratings (1) 1. absolute maximum continuous ratings are those maximum values beyond which damage to t he device may occur. exposure to these conditions or conditions beyond th ose indicated may adversely affect device re liability. functional operation under absolute-ma ximum-rated conditions is not implied. symbol characteristics min max unit condition v cc supply voltage -0.3 4.6 v v in dc input voltage -0.3 v cc +0.3 v v out dc output voltage -0.3 v cc +0.3 v i in dc input current $ 20 ma i out dc output current $ 50 ma t s storage temperature -55 125 ! c
idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 4 mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom advanced clock drivers devices 4 freescale semiconductor mpc9315 table 4. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc %# 2 v mm esd (machine model) 200 v hbm esd (human body model) 2000 v lu latch-up 200 ma c pd power dissipation capacitance 10 pf per output c in input capacitance 4.0 pf inputs table 5. dc characteristics (v cc = 3.3 v 5%, t a = -40 to 85c) symbol characteristics min typ max unit condition v ih input high voltage 2.0 v cc + 0.3 v lvcmos v il input low voltage 0.8 v lvcmos v oh output high voltage 2.4 v i oh = ?24 ma (1) 1. the mpc9315 is capable of driving 50 " transmission lines on the incident edge. each output drives one 50 " parallel terminated transmission line to a te rmination voltage of v tt . alternatively, the device drives up to two 50 " series terminated transmission lines. v ol output low voltage 0.55 0.30 v v i ol = 24 ma (1) i ol = 12 ma z out output impedance 14 - 17 " i in input current (2) 2. inputs have pull-up or pull-down resistors affecting the input current. $ 200 & a v in = v cc or gnd i cca maximum pll supply current 3.5 7.0 ma v cca pin i ccq maximum quiescent supply current 1.0 ma all v cc pins
advanced clock drivers devices freescale semiconductor 5 mpc9315 table 6. ac characteristics (v cc = 3.3 v 5%, t a = -40 to 85c) (1) 1. ac characteristics apply for par allel output termination of 50 " to v tt . symbol characteristics min typ max unit condition f ref input frequency # 1 feedback # 2 feedback # 4 feedback pll bypass mode 100 (2) 37.50 18.75 0 2. the vco range in # 1 feedback configuration (e.g. qax connected to fbx and fsela = 0) is limited to 100 ' f vco ' 160 mhz. please see next revision of the mpc9315 for improved vco frequency range. 160 80 40 tbd mhz mhz mhz mhz pll locked pll locked pll locked v cca = gnd f vco vco lock range 75 (2) 160 mhz f max maximum output frequency # 1 output # 2 output # 4 output 75 37.50 18.75 160 80 40 mhz mhz mhz f refdc reference input duty cycle 25 75 % t r , t f clk0, clk1 input rise/fall time 1.0 ns 0.8 to 2.0 v t ( ( ) propagation delay clk0 or clk1 to fb (static phase offset) -150 +150 ps pll locked t sk( ( ) output-to-output skew within one bank any output 80 120 ps ps dc output duty cycle 45 50 55 % t r , t f output rise/fall time 0.1 1.0 ns 0.55 to 2.4 v t plz, hz output disable time 10 ns t pzl, lz output enable time 10 ns bw pll closed loop bandwidth # 1 feedback # 2 feedback # 4 feedback tbd 2.0 - 20 0.6 - 6.0 mhz mhz mhz t jit(cc) cycle-to-cycle jitter (1 ) ) 10 22 ps rms value t jit(per) period jitter (1 ) ) 8.0 15 ps rms value t jit( ( ) i/o phase jitter (1 ) ) 8.0 - 25 (3) 3. i/o jitter depends on vco frequency. please see application section for i/o jitter versus vco frequency characteristics. tbd ps rms value t lock maximum pll lock time 1.0 ms table 7. dc characteristics (v cc = 2.5 v 5%, t a = -40 to 85c) symbol characteristics min typ max unit condition v ih input high voltage 1.7 v cc + 0.3 v lvcmos v il input low voltage 0.7 v lvcmos v oh output high voltage 1.8 v i oh = ?15 ma (1) 1. the mpc9315 is capable of driving 50 " transmission lines on the inciden t edge. each output drives one 50 " parallel terminated transmission line to a termination voltage of v tt . alternatively, the device drives up to two 50 " series terminated transmission lines. v ol output low voltage 0.6 v i ol = 15 ma z out output impedance 17 - 20 " i in input current (2) 2. inputs have pull-up or pull-down resistors affecting the input current. $ 200 & a v in = v cc or gnd i cca maximum pll supply current 2.0 5.0 ma v cca pin i ccq maximum quiescent supply current 1.0 ma all v cc pins idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 5 mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom
idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 6 mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom advanced clock drivers devices 6 freescale semiconductor mpc9315 table 8. ac characteristics (v cc = 2.5 v 5%, t a = -40 to 85c) (1) 1. ac characteristics apply for parallel output termination of 50 " to v tt . symbol characteristics min typ max unit condition f ref input frequency # 2 feedback # 4 feedback pll bypass mode 37.50 18.75 0 80 40 tbd mhz mhz mhz pll locked pll locked vcca = gnd f vco vco lock range 75 (2) 2. # 1 feedback is responsible for v cc = 2.5 v operation. please see application section fo r i/o jitter versus vco frequency characteristics. 160 (2) mhz f max maximum output frequency # 1 output # 2 output # 4 output 75 37.50 18.75 160 80 40 mhz mhz mhz f refdc reference input duty cycle 25 75 % t r , t f clk0, clk1 input rise/fall time 1.0 ns 0.7 to 1.7 v t ( ( ) propagation delay clk0 or clk1 to fb (static phase offset) -150 +150 ps pll locked t sk( ( ) output-to-output skew within one bank any output 80 120 ps ps dc output duty cycle 45 50 55 % t r , t f output rise/fall time 0.1 1.0 ns 0.55 to 2.4 v t plz, hz output disable time 12 ns t pzl, lz output enable time 12 ns bw pll closed loop bandwidth # 2 feedback # 4 feedback 1.0 - 10 0.4 - 3.0 mhz mhz t jit(cc) cycle-to-cycle jitter (1 ) ) 10 22 ps rms value t jit(per) period jitter (1 ) ) 8.0 15 ps rms value t jit( ( ) i/o phase jitter (1 ) ) 10 - 25 (3) 3. i/o jitter depends on vco frequency. plea se see application section for i/o ji tter versus vco frequency characteristics. tbd ps rms value t lock maximum pll lock time 1.0 ms
mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom advanced clock drivers devices freescale semiconductor 7 mpc9315 applications information programming the mpc9315 the pll of the mpc9315 supports output clock frequencies from 18.75 to 160 mhz. different feedback and output divider configurations can be used to achieve the desired input to output frequency relationship. the feedback frequency and divider should be used to situate the vco in the frequency range between 75 and 160 mhz for stable and optimal operation. the fsela, fselb, fselc pins select the desired output clock frequencies. possible frequency ratios of the reference clock input to the outputs are 1:1, 1:2, 1:4 as well as 2:1 and 4:1, ta b l e 9 , table 10 , and table 11 illustrate the various output configurations and frequency ratios supported by the mpc931 5. psela controls the output phase of the qa0 and qa1 outputs, allowing the user to generate inverted clock signals synchronous to non-inverted clock signals. see also example configurations for the mpc9315 for further reference. table 9. output frequency relationship for qa0 connected to fb0 (1) 1. output frequency relationship with respect to input reference frequency clk. inputs outputs fsela fselb fselc qa0, qa1 qb0?qb3 qc0, qc1 0 0 0 clk clk clk # 2 0 0 1 clk clk clk # 4 0 1 0 clk clk # 2 clk # 2 0 1 1 clk clk # 2 clk # 4 1 0 0 clk 2 * clk clk 1 0 1 clk 2 * clk clk # 2 1 1 0 clk clk clk 1 1 1 clk clk clk # 2 table 10. output frequency relationship for qb0 connected to fb0 (1) 1. output frequency relationship with respect to input reference frequency clk. inputs outputs fsela fselb fselc qa0, qa1 qb0?qb3 qc0, qc1 0 0 0 clk clk clk # 2 0 0 1 clk clk clk # 4 0 1 0 2 * clk clk clk 0 1 1 2 * clk clk clk # 2 1 0 0 clk # 2 clk clk # 2 1 0 1 clk # 2 clk clk # 4 1 1 0 clk clk clk 1 1 1 clk clk clk # 2 table 11. output frequency relationship for qc0 connected to fb0 (1) 1. output frequency relationship with respect to input reference frequency clk. inputs outputs fsela fselb fselc qa0, qa1 qb0?qb3 qc0, qc1 0 0 0 2 * clk 2 * clk clk 0 0 1 4 * clk 4 * clk clk 0 1 0 2 * clk clk clk 0 1 1 4 * clk 2 * clk clk 1 0 0 clk 2 * clk clk 1 0 1 2 * clk 4 * clk clk 1 1 0 clk clk clk 1 1 1 2 * clk 2 * clk clk idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 7
idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 8 mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom advanced clock drivers devices 8 freescale semiconductor mpc9315 example configurations for the mpc9315 figure 3. mpc9315 default configuration figure 4. mpc9315 zero delay buffer configuration figure 5. mpc9315 180 phase inversion configuration figure 6. mpc9315 x4 multiplier configuration mpc9315 160 mhz 80 mhz 80 mhz (feedback) clk0 clk1 ref_sel fb0 fb1 fbsel fsela fselb fselc psela 40 mhz mpc9315 default conf iguration (feedback of qb3 = 100 mhz). all control pins are left open. mpc9315 75 mhz 75 mhz qa0 qa1 qb0 qb1 qb2 qb3 qc0 qc1 clk0 clk1 ref_sel fb0 fb1 fbsel fsela fselb fselc psela 75 mhz mpc9315 1:1 frequency configuration (feedback of qb3 = 75 mhz). fsela = h, f selc = l. all other control pins are left open. mpc9315 fref = 33 mhz 66 mhz inv, 66 mhz qa0 qa1 qb0 qb1 qb2 qb3 qc0 qc1 clk0 clk1 ref_sel fb0 fb1 fbsel fsela fselb fselc psela 33 mhz 1 1 mpc9315 1:1 frequency conf iguration (feedback of qc1 = 33 mhz). fsela = psel a = h. all other control pins are left open. mpc9315 76 mhz 38 mhz qa0 qa1 qb0 qb1 qb2 qb3 qc0 qc1 clk0 clk1 ref_sel fb0 fb1 fbsel fsela fselb fselc psela 19 mhz mpc9315 4x, 2x, 1x frequency configuration (feedback of qc1 = 19 mhz). all control pins are left open. frequency range min max input 37.50 mhz 80 mhz qa outputs 75.00 mhz 160 mhz qb outputs 37.50 mhz 80 mhz qc outputs 18.75 mhz 40 mhz frequency range min max input 37.50 mhz 80 mhz qa outputs 37.50 mhz 80 mhz qb outputs 37.50 mhz 80 mhz qc outputs 37.50 mhz 80 mhz frequency range min max input 18.75 mhz 40 mhz qa outputs 37.50 mhz 80 mhz qb outputs 37.50 mhz 80 mhz qc outputs 18.75 mhz 40 mhz frequency range min max input 18.75 mhz 40 mhz qa outputs 75.00 mhz 160 mhz qb outputs 37.50 mhz 80 mhz qc outputs 18.75 mhz 40 mhz 0 1 qa1 qb1 qb2 qb0 qb3 qa0 qc0 qc1 fref = 80 mhz 75 mhz (feedback) fref = 75 mhz 33 mhz (feedback) 19 mhz (feedback) fref = 19 mhz
idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 9 mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom advanced clock drivers devices freescale semiconductor 9 mpc9315 using the mpc9315 in zero-delay applications the external feedback option of the mpc9315 pll allows for its use as a zero delay buffer. the pll aligns the feedback clock output edge with the clock input reference edge and virtually eliminates the propagation delay through the device. the remaining insertion delay (skew error) of the mpc9315 in zero-delay applications is measured between the reference clock input and any output. this effective delay consists of the static phase offset (spo or t ( ( ) ), i/o jitter (t jit( ( ) , phase or long-term jitter), feedback path delay and the output-to-output skew (t sk(o) relative to the feedback output. calculation of part-to-part skew the mpc9315 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. if the reference clock inputs (tclk or pclk) of two or more mpc9315 are connected together, the maximum overall timing uncertainty from the common tclk input to any output is: t sk(pp) = t ( ( ) + t sk(o) + t pd, line(fb) + t jit( ( ) * cf this maximum timing uncertainty consists of 4 components: static phase offset, output skew, feedback board trace delay and i/o (phase) jitter: due to the statistical nature of i/o jitter, an rms value (1 ) ) is specified. i/o jitter numbers for other confidence factors (cf) can be derived from table 12 . the feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. in the following example calculation, an i/o jitter confidence factor of 99.7% ( $ 3 ) ) is assumed, resulting in a worst case timing uncertainty from input to any output of ?300 ps to +300 ps relative to tclk (v cc =3.3v and f vco = 160 mhz): t sk(pp) = [?150ps...150ps] + [?150ps...150ps] + [(10ps @ ?3)...(10ps @ 3)] + t pd, line(fb) t sk(pp) = [?300ps...300ps] + t pd, line(fb) above equation uses the ma ximum i/o jitter number shown in the ac characteristic table for v cc =3.3v (10 ps rms). i/o jitter is frequency-dependant with a maximum at the lowest vco frequency (160 mhz for the mpc9315). applications using a higher vco frequency exhibit less i/o jitter than the ac characteristic limit. the i/o jitter characteristics in figure 8 and figure 9 can be used to derive a smaller i/o jitter number at the specific vco frequency, resulting in tighter timing limi ts in zero-delay mode and for part-to-part skew t sk(pp) . table 12. confidence factor cf cf probability of clock edge within the distribution $ 1 ) 0.68268948 $ 2 ) 0.95449988 $ 3 ) 0.99730007 $ 4 ) 0.99993663 $ 5 ) 0.99999943 $ 6 ) 0.99999999 figure 7. mpc9315 ma x. device-to-device skew t pd,line(fb) t jit( ( ) +t sk(o) ?t (y) +t ( ( ) t jit( ( ) +t sk(o) t sk(pp) max. skew qfb device 1 any q device 1 qfb device2 any q device 2 tclk common figure 8. max. i/o jitter (r ms) versus frequency for v cc = 2.5 v 30 25 20 15 10 5 0 75 100 125 150 175 200 vco frequency [mhz] t jit(y) [ps] ms i/o jitter (rms) ve rsus vco frequency f igure 9. max. i/o jitter (rms ) versus frequency for v cc = 3.3 v 30 25 20 15 10 5 0 75 100 125 150 175 200 t jit(y) [ps] ms i/o jitter (rms) versus vco frequency vco frequency (mhz)
advanced clock drivers devices 10 freescale semiconductor mpc9315 power supply filtering the mpc9315 is a mixed analog/digital product. its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. noise on the v cca (pll) power supply impacts th e device characteristics, for instance i/o jitter. the mpc9315 provides separate power supplies for the output buffers (v cc ) and the phase-locked loop (v cca ) of the device. the purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. in a digital system environm ent where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. the simple but effective form of isolation is a power supply filter on the v cca pin for the mpc9315. figure 10 illustrates a typical power supply filter scheme. the mpc9315 frequency and phase stability is most susceptible to noise with spectral content in the 100 khz to 20 mhz range. therefore the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc volt age drop across the series filter resistor r f . from the data sheet, the i cca current (the current sourced through the v cca pin) is typically 3 ma (5 ma maximum), assuming that a minimum of 2.325 v (v cc = 3.3 v or v cc = 2.5 v) must be maintained on the v cca pin. the resistor r f shown in figure 10 must have a resistance of 270 " (v cc = 3.3 v) or 9-10 " (v cc = 2.5 v) to meet the voltage drop criteria. the minimum values for r f and the filter capacitor c f are defined by the required filter characteristics: the rc filter should provide an attenuation greater than 40 db for noise whose spectral content is above 100 khz. in the example rc filter shown in figure 10 , the filter cut-off frequency is around 3-5 khz and the noise attenuation at 100 khz is better than 42 db. as the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. although the mpc9315 has several design features to mi nimize the susceptibility to power supply noise (isolated power and grounds and fully differential pll) there still may be applications in which overall performance is being degraded due to system power supply noise. the power supply filter schemes discussed in this section should be adequate to eliminate power supply noise-related problems in most designs. driving transmission lines the mpc9315 clock driver was designed to drive high speed signals in a terminated transmission line environment. to provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. with an output impedance of less than 20 "+ the drivers can drive either parallel or series terminated transmission lines. for more information on transmission lines, the reader is referred to freescale application note an1091. in most high performance clock networks, point-to-point distribution of si gnals is the method of choice. in a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. the parallel technique terminates the signal at the end of the line with a 50 " resistance to v cc # 2. this technique draws a fairly high level of dc current and thus only a single terminated line can be driven by each output of the mpc9315 clock driver. for the series terminated case, however, there is no dc current draw; thus, the outputs can drive multiple series terminated lines. figure 11 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. when taken to its extreme, the fanout of the mpc9315 clock driver is effectively doubled due to its capability to drive multiple lines. the waveform plots in figure 11 show the simulation results of an output driving a si ngle line versus two lines. in figure 10. v cca power supply filter v cca v cc mpc9315 r f = 270 " for v cc = 3.3 v c f r f v cc c f = 1 & f for v cc = 3.3 v c f = 22 & f for v cc = 2.5 v r f = 9?10 " for v cc = 2.5 v 10 nf 33...100 nf figure 11. single versus dual transmission lines 14 " in mpc9315 output buffer r s = 36 " z o = 50 " 14 " in mpc9315 output buffer r s = 36 " z o = 50 " r s = 36 " z o = 50 " outa outb0 outb1 idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 10 mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom
idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 11 mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom advanced clock drivers devices freescale semiconductor 11 mpc9315 both cases, the drive capabili ty of the mpc9315 output buffer is more than sufficient to drive 50 " transmission lines on the incident edge. note from the delay measurements in the simulations, a delta of only 43 ps exists between the two differently loaded outputs. this suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the mpc9315. the output waveform in figure 12 shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. the parallel combination of the 36 " series resistor plus the output impedance does not match the parallel combination of the line impedances. the voltage wave launched down the two lines will equal: v l =v s (z 0 # (r s +r 0 + z 0 )) z 0 =50 %" || 50 " r s =36 %" || 36 " r 0 =14 %" v l = 3.0 (25 # (18+17+25) =1.31 v at the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 v. it will then increment towards the quiescent 3.0 v in steps separated by one round trip delay (in this case 4.0 ns). since this step is well above the threshold region, it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. to better match the impedances when driving multiple lines, the situation in figure 13 should be used. in this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. figure 12. single versus dual line termination waveforms time (ns) voltage (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 10 12 14 outb t d = 3.9386 outa t d = 3.8956 in figure 13. optimized dual line termination 14 " mpc9315 output buffer r s = 22 " z o = 50 " r s = 22 " z o = 50 " 14 "% + 22 " || 22 " = 50 " || 50 " 25 " = 25 " figure 14. clk0, clk1 mpc9315 ac test reference pulse generator z = 50 " z o = 50 " z o = 50 " v tt v tt r t = 50 " r t = 50 " mpc9315 dut
advanced clock drivers devices 12 freescale semiconductor mpc9315 figure 15. propagation delay (t ( ( ) , spo) test reference figure 16. output duty cycle (dc) figure 17. output-to-output skew t sk(o) the pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device the time from the pll controlled edge to the non controlled edge, divided by the time between pll controlled edges, expressed as a percentage v cc v cc #% 2 gnd v cc v cc #% 2 gnd t sk(o) v cc gnd t p t 0 dc = t p /t 0 x 100% v cc v cc #% 2 gnd v cc v cc #% 2 gnd t ( ( ) clk0, 1 fb0, 1 v cc #%, figure 18. cycle-to-cycle jitter figure 19. period jitter the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs the deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles t n t n+1 t jit(per) = | t n ?1 / f 0 | t 0 t f t r v cc =3.3 v v cc =2.5 v 2.4 1.8 v 0.55 0.6 v figure 20. i/o jitter figure 21. output transition time test reference t jit( ( ) = | t 0 ?t 1 mean | tclk0, 1 fb0, 1 the deviation in t 0 for a controlled edge with respect to a t 0 mean in a random sample of cycles t jit(cc) = |t n ?t n+1 | idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 12 mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom
idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 13 mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom advanced clock drivers devices freescale semiconductor 13 mpc9315 package dimensions case 873a-04 issue c 32-lead lqfp package page 1 of 3
mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom advanced clock drivers devices 14 freescale semiconductor mpc9315 package dimensions case 873a-04 issue c 32-lead lqfp package page 2 of 3 idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 14
advanced clock drivers devices freescale semiconductor 15 mpc9315 package dimensions case 873a-04 issue c 32-lead lqfp package page 3 of 3 idt? 2.5 v and 3.3 v cmos pll clock generator and driver freescale timing solutions organization has been acquired by integrated device technology, inc mpc9315 15 mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom
mpc9315 2.5 v and 3.3 v cmos pll clock generator and driver netcom mpc92459 900 mhz low voltage lvds clock synthesizer netcom ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future networks. contact: www.idt.com part numbers insert product name and document title netcom

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